A track-and-hold amplifier circuit, which may be also called sample-and-hold amplifier circuit, for example may be used to interface a continuously changing analog signal to a subsequent circuit such as an analog-to-digital converter (ADC). The purpose of the track-and-hold amplifier circuit is to hold the analog value steady for a short time while the subsequent analog-to-digital converter or any other subsequent circuit performs some operation, i.e. for example to sample the value of the analog signal, which takes a little time.
Track and hold amplifier circuits and successive analog to digital converters are the most dominant blocks in an analog front end, because they are hard to design, dominant in power consumption and thus require most of the design time.
Various concepts of track and hold amplifier circuits have been discussed in the prior art, such as in W. Black and D. Hodges, “Time Interleaved converter arrays”, IEEE Journal of solid-state circuits, Vol. SC-15, No. 6, pp. 1022-1029, December 1980, or N. Kurosawa et al., “Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems”, IEEE Journal of Solid-state Circuits, Vol. 48, No. 3, pp. 261-271, March 2001, or G. Leger et al., “Impact of Random Channel Mismatch on the SNR and SFDR of Time-Interleaved ADCs”, IEEE Journal of Solid-State Circuits, Vol. 51, No. 1, pp. 140-150, January 2004, or J. Elbornsson et al., “Blind Equalization of Time Errors in a Time-Interleaved ADC System”, IEEE Transactions on Signal Processing, Vol. 53, No. 4, pp. 1413-1424, April 2005, or P. Lim and B. Wooley, “A High-Speed Sample-and-Hold Technique Using a Miller Hold Capacitance”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, pp. 643-651, April 1991.
The principles and in particular the problem underlying the current invention will be explained in the following examples of prior art.
FIG. 1A depicts the schematics of a conventional closed-loop track-and-hold amplifier (THA) circuit 100 comprising a first and a second stage 110, 120. The first stage 110 comprises an operational amplifier 130 receiving an input voltage Vin at its negative input. The amplifier's output is coupled to the second stage 120, which is adapted to hold a value—of the input signal—for a period of time. In this example the second stage comprises an inverter 140 outputting an output signal Vout and a Miller capacitor 150 coupled between in- and output of the inverter 140 is used to store the analog value. Feedback path 160 couples the output signal Vout to the non-inverting input of the operational amplifier 130. A first and a second switch 170, 171 are arranged in the feedback path 160 and between the operational amplifier and the inverter respectively.
Switches 170, 171 are switching synchronously according to a clock signal φ1 shown in FIG. 1B. The clock signal toggles between a low state and a high state thus clocking the switches 170, 171 to close and to open accordingly. Both switches 170, 171 close when the clock signal φ1 exceeds a voltage Vthreshold and accordingly open when the clock signal drops below the threshold voltage. When the switches are closed the output signal Vout tracks the input signal and the capacitor 150 is charged to the voltage of the output signal. When both switches are open the capacitor holds the voltage of the output signal steady until the switches are closed again. Accordingly the output signal tracks or in other words follows the input signal when the clock signal exceeds the threshold voltage and holds the voltage of the output signal when the clock signal drops below the threshold voltage.
The dotted line in FIG. 1C illustrates an input signal 180 as a function of time, which in this example is a sinusoidal, continuous signal. Output signal 190 as output from track-and-hold circuit 100 follows the input signal during track intervals denoted with T, such that the massive line denoting output signal 190 matches and thus covers the dotted line of input signal 180 in track intervals. When the switches 170, 171 are open, that is during hold intervals denoted with H, then the output signal is kept constant, hence the signals differ. As soon as the switches are closed again, the output signal 190 jumps to follow the input signal 180, so that there are jumps or stairs 171 in the signal waveform at transitions from hold to track intervals.
The track-and-hold circuit shows good and accurate tracking of the input signal due to the feedback path 160, as long as there is sufficient loop gain at the frequency of interest. As switch 171, which is the sampling switch, is located at a point in the circuit with little signal swing, the on-resistance and channel charge show very little dependence from the input signal and hence will not cause considerable distortion of the output signal. However the circuit holds the amplitude value of the input signal only during hold intervals, i.e. only during half of the time.
FIG. 2A depicts a circuit 200 as known from prior art comprising a first and a second identical track-and-hold branch 210, 220 in parallel having similarities to the circuit discussed above. The branches each comprise a first and a second stage, wherein the first stages are each coupled to the input signal Vin and the output signals Vo1 and Vo2 of branches 210, 220 are coupled via switches 230, 231 to form a single output signal Vout.
FIG. 2B depicts clock signals φ1 and φ2 which are similar to the clock signal of FIG. 1C and interleaved in time by one half clock cycle. Accordingly clock signal φ1 is in its high state when φ2 is low and vice versa. The switches of 210 and switch 231 are clocked by clock signal φ1 and switches of 220 as well as switch 230 are clocked by φ2 accordingly. Thus branches 210, 220 are clocked with different phases of the two non-overlapping clock signals φ1 and φ2, hence interleaving the branches 210 and 220 in time. That is, as is apparent from the clock signals φ1 and φ2, branch 210 is in hold mode and its output is coupled via switch 230 to the overall output while branch 220 is in track mode and decoupled from the overall output Vout. Subsequently and when the clock signals toggle the output of branch 220 is coupled to the overall output while the output of branch 210 is decoupled from overall output signal Vout.
The massive line in FIG. 2C depicts the resulting overall output signal Vout 260 as a function of time, while the input signal Vin 250 is shown as the dotted line. The output signal Vout has been constructed from the output of branches 210, 220 by switching the switches 230, 231 appropriately to interleave the output signals Vo1 and Vo2 during their individual hold interval. As shown in the drawing output signal Vout now consists of stairs being discrete values connected by signal jumps, wherein each stair is a value of one of the circuits 210, 220 during its individual hold interval.
The number of discrete values is defined by the frequency of the clock signals, wherein a higher clock frequency, which is the sampling frequency Fs, causes more discrete values per time. The output signal will thus follow the input more closely.
The circuits 210, 220 furthermore comprise offset voltages, wherein the effective offset voltages of the circuits are dominated by the offset voltages of the input stages, i.e. Voff1 and Voff2. The offset voltages Voff12 and Voff22 of the second amplifiers or inverters respectively are suppressed by the loop-gain.
However due to fabrication tolerances the operational amplifiers have different offset voltages. When cycling through the parallel track-and-hold branches the different offset voltages cause tones at a frequency of Fs/N, with Fs being the sampling frequency and N being the number of parallel branches, because for each sampling interval the next of the parallel branches having its own offset voltage is coupled to the output.
A second problem is caused by the individual gain-errors of the parallel branches, which produce tones at Fs/N+Fin and Fs/N−Fin, with Fin being the frequency of interest.
In particular with increasing N this tone will be in the signal band of interest and thus will degrade the signal to noise ratio (SNR) of the circuit and ultimately the Effective Number of Bits (ENOB) of the Analog Front End. With offset voltages in the order of millivolts and signal swings in the order of several hundreds of millivolts, this will put an upper limit around 45 dB to 50 dB for the SNR of the analog front end, thus limiting the ENOB to 7 or 8 bits at the output of an analog to digital converter.
Accordingly there is a need for a track and hold amplifier avoiding the above mentioned tones.